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(R)
HS-201HSRH
Data Sheet March 24, 2006 FN4874.1
Radiation Hardened High Speed, Quad SPST, CMOS Analog Switch
The HS-201HSRH is a monolithic CMOS analog switch featuring power-off high input impedance, very fast switching speeds and low ON resistance. Fabrication on our DI RSG process assures SEL immunity and only very slight sensitivity to low dose rate (ELDRS). These Class V/Q devices are tested and guaranteed for 300krad (Si) total dose performance. Power-off high input impedance enables the use of this device in redundant circuits without causing data bus signal degradation. ESD protection, overvoltage protection, fast switching times, low ON resistance, and guaranteed radiation hardness, make the HS-201HSRH ideal for any space application where improved switching performance is required. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center (DSCC). The SMD numbers listed here must be used when ordering flight units. Detailed electrical specifications for this device are contained in SMD 5962-99618. A "hot-link" is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp
Features
* Electrically Screened to DSCC SMD 5962-99618 * QML Qualified per MIL-PRF-38535 * Radiation Performance - Guaranteed Total Dose Performance . . . . . 300krad (Si) - SEL Immune. . . . . . . . . . . . . . . . . . . . .DI RSG Process * Overvoltage Protection (Power On, Switch Off) . . . . . . 30V * Power Off High Impedance . . . . . . . . . . . . . . . . . . . 17V * Fast Switching Times - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110ns (Max) - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80ns (Max) * Low "ON" Resistance . . . . . . . . . . . . . . . . . . . 50 (Max) * Pin Compatible with Industry Standard 201 Types * Operating Supply Range . . . . . . . . . . . . . . . . . 10V to 15V * Wide Analog Voltage Range (15V Supplies) . . . . . . . 15V * TTL Compatible
Applications
* High Speed Multiplexing * Sample and Hold Circuits * Digital Filters
Pinout
HS1-201HSRH, SBDIP (CDIP2-T16) HS9-201HSRH, FLATPACK (CDFP4-F16) TOP VIEW
A1 1 OUT1 2 IN1 3 V- 4 GND 5 IN4 6 OUT4 7 A4 8 16 A2 15 OUT2 14 IN2 13 V+ 12 NC 11 IN3 10 OUT3 9 A3
* Operational Amplifier Gain Switching Networks * Integrator Reset Circuits
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HS-201HSRH Ordering Information
ORDERING NUMBER 5962F9961801VEC 5962F9961801QEC 5962F9961801VXC 5962F9961801QXC 5962F9961801V9A HS1-201HSRH/PROTO HS9-201HSRH/PROTO INTERNAL MKT. NUMBER HS1-201HSRH-Q HS1-201HSRH-8 HS9-201HSRH-Q HS9-201HSRH-8 HS0-201HSRH-Q HS1-201HSRH/PROTO HS9-201HSRH/PROTO PART MARKING Q 5962F9961801VEC Q 5962F9961801QEC Q 5962F9961801VXC Q 5962F9961801QXC HS1-201HSRH/PROTO HS9-201HSRH/PROTO TEMP. RANGE (C) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld SBDIP 16 Ld SBDIP 16 Ld Flatpack 16 Ld Flatpack 16 Ld SBDIP 16 Ld Flatpack PKG. DWG. # D16.3 D16.3 K16.A K16.A D16.3 K16.A
Die Characteristics
DIE DIMENSIONS 2790m x 4950m (110 mils x 195 mils) Thickness: 483m 25.4m (19 mils 1 mil) INTERFACE MATERIALS Glassivation Type: Phosphorus Silicon Glass (PSG) Thickness: 8.0kA +/-1.0kA Metallization Type: Ti/AlCu Thickness: 16.0kA +/- 2kA Substrate Rad Hard Silicon Gate, Dielectric Isolation Backside Finish Silicon ASSEMBLY RELATED INFORMATION Substrate Potential Unbiased (DI) ADDITIONAL INFORMATION Worst Case Current Density <2.0 x 105 A/cm2 Transistor Count 328
Metallization Mask Layout
HS-201HSRH
OUT4
IN4
GND
V-
IN1
OUT1
A4
A1
A3
A2
OUT3
IN3
V+
IN2
OUT2
2
FN4874.1 March 24, 2006
HS-201HSRH Ceramic Metal Seal Flatpack Packages (Flatpack)
A
K16.A MIL-STD-1835 CDFP4-F16 (F-5A, CONFIGURATION B)
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE INCHES SYMBOL MIN 0.045 0.015 0.015 0.004 0.004 0.245 0.130 0.030 MAX 0.115 0.022 0.019 0.009 0.006 0.440 0.285 0.315 A b b1 c c1 MILLIMETERS MIN 1.14 0.38 0.38 0.10 0.10 6.22 3.30 0.76 1.27 BSC 0.20 6.35 0.66 0.13 16 0.38 9.40 1.14 0.04 MAX 2.92 0.56 0.48 0.23 0.15 11.18 7.24 8.00 NOTES 3 3 7 2 8 6 Rev. 1 2-20-95
e
PIN NO. 1 ID AREA
A
-A-
-B-
D
S1 b E1 0.004 M Q A -C-HL E3 SEATING AND BASE PLANE c1 LEAD FINISH E2 E3 L H A-B S DS E 0.036 M H A-B S C -DDS
D E E1 E2 E3 e k L Q S1 M N
0.050 BSC 0.008 0.250 0.026 0.005 16 0.015 0.370 0.045 0.0015
BASE METAL b1 M M (b) SECTION A-A
(c)
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH
3
FN4874.1 March 24, 2006
HS-201HSRH Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1 -A-DBASE METAL M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS b1 M (b) SECTION A-A (c) LEAD FINISH
D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C)
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c c1 D E e eA eA/2 L Q S1 S2 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.840 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 21.34 7.87 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 0.13 90o 16 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 4/94
E
eA e eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 0.005 90o 16 0.200 0.060 105o 0.015 0.030 0.010 0.0015
ccc M C A - B S D S
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH.
aaa bbb ccc M N
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 4
FN4874.1 March 24, 2006

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